By Himanshu Bhatnagar
The emphasis of this publication is on real-time software of Synopsys instruments, used to strive against a variety of difficulties obvious at VDSM geometries. Readers should be uncovered to an efficient layout technique for dealing with complicated, sub-micron ASIC designs. value is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to format, actual synthesis, and static timing research. At each one step, difficulties comparable to every section of the layout circulation are pointed out, with recommendations and work-around defined intimately. additionally, the most important concerns comparable to structure, which include clock tree synthesis and back-end integration (links to format) also are mentioned at size. additionally, the publication includes in-depth discussions at the foundation of Synopsys know-how libraries and HDL coding kinds, precise in the direction of optimum synthesis resolution.
aim audiences for this publication are practising ASIC layout engineers and masters point scholars venture complicated VLSI classes on ASIC chip layout and DFT techniques.
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Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime® by Himanshu Bhatnagar